1. Field of the Invention
The present invention generally relates to trench isolation structures in integrated circuits. More particularly, the present invention relates to a method for forming shallow trench isolation (STI) structures in integrated circuits having high integration density.
2. Description of the Related Art
Conventional semiconductor design uses a trench-isolation type method of isolating elements on an integrated circuit. In a trench-isolation method, a trench with rounded corners is formed on the surface of a semiconductor substrate to embed an insulator in the substrate. This method helps to make semiconductor devices smaller and to enhance the reliability of such devices, especially the gate reliability of such devices. An example of this method is disclosed in U.S. Pat. No. 4,923,821, and "Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation (STI)" by Tai-su Park, et al., published in a Proceeding of the IEEE, IEDM 1996, p 747-750.
FIG. 1 is a flow chart showing the steps in a conventional trench-isolation type fabrication method. FIGS. 2A through 2L are cross-sectional views showing the semiconductor substrate during the process shown in FIG. 1.
As shown in FIGS. 1 and 2A, the process begins by growing a pad oxide layer 3 on a semiconductor substrate 1 (Step 10). The process then continues by depositing and patterning a silicon nitride layer 5 over the pad oxide layer 3 (Step 15).
As shown in FIG. 2B, a trench 7 is then etched out of the semiconductor substrate 1 using the patterned silicon nitride layer 5 as a mask (Step 20). As shown in FIGS. 2C and 2D, a sidewall-insulating layer 9 is then formed on the bottom and inside walls of the trench 7 and a trench-insulating layer 11 is formed in the trench 7 (Step 25).
The process of forming the sidewall-insulating layer 9 on the bottom and inside walls of the trench 7 and the trench-insulating layer 11 in the trench 7 includes a number of sub-steps. First, the sidewall-insulating layer 9, shown in FIG. 2C, is grown on the bottom and inside walls of the trench 7 (Step 100). The sidewall-insulating layer 9 is preferably grown in an O.sub.2 ambient atmosphere by oxidizing the exposed silicon surface. The sidewall-insulating layer 9 functions to reduce the trench etching damage and passivate the exposed silicon surface.
As shown in FIG. 2D, a trench-insulating layer 11 is then deposited into the trench 7, and over the silicon nitride layer 5 (Step 110). As noted above, the trench-insulating layer is often a CVD oxide such as SiO.sub.2.
The trench-insulating layer 11 is then reduced by a chemical-mechanical polishing (CMP) process using the silicon nitride layer 5 as a stopper (Step 120), as shown in FIG. 2E. This leaves the trench 7 filled with the trench-insulating layer 11, and the top of the trench-insulating layer 11 even with the top of the silicon nitride layer 5.
Finally, the trench-insulating layer 11 is annealed (densified) in an N.sub.2 or Ar gas ambient. In this annealing process, a high temperature is required to lower junction current by annealing the stress. A high temperature for the annealing also avoids the problems of leaky junctions, defect generation via the junctions, and too high wet etch rate of the CVD (Step 130). Preferably, the temperature is kept above 1150.degree. C. This densifies the trench-insulating layer 11 and thus increases its resistance to wet etching.
After the a sidewall-insulating layer 9 and the trench-insulating layer 11 are formed, the active silicon nitride layer 5 is then removed using a wet etching process, as shown in FIG. 2F (Step 30). Since the trench-insulating layer 11 has previously been annealed in step 130, its etching rate is reduced and the wet etching process results in only minimal etching of the trench-insulating layer 11. Then, as shown in FIG. 2G, the pad oxide layer 3 is also removed by wet etching (Step 35).
A sacrificial oxide layer 13 is then grown over the semiconductor substrate using a thermal oxidation method in an O.sub.2 or H.sub.2 O ambient (Step 40), as shown in FIG. 2H. Ion implantation 15 is then performed to create heavily-doped regions 17 (Step 45), and the sacrificial oxide layer 13 is then removed (Step 50), as shown in FIG. 2I. The sacrificial oxide 13 is usually removed by another wet etching process, which also etches away an additional part of the trench-insulating layer 11.
As shown in FIG. 2J, a gate oxide layer is then grown over the substrate I (Step 55). During this step, the oxide layer naturally goes flat within an optimum process condition.
Finally, as shown in FIG. 2K, the gate electrode 21 is deposited over the gate oxide layer 19 and the trench-isolating layer 11 (Step 60).
FIG. 2L shows the same structure as FIG. 2K, except that the sidewall-insulating layer 9, the trench-isolation layer 11, and the gate oxide layer 19 are all conceptually identified as a single unified oxide layer 23. Since all of these three layers are oxide layers, and all serve a similar function, it is helpful at times to consider then functionally as a single layer rather than three separate layers.
In STI structures formed by the conventional method, chemical-vapor deposition (CVD) oxides are most commonly used as a trench embedding material. After such a CVD oxide is filled into the trench formed in the semiconductor substrate, a high temperature annealing process is carried out to densify the embedded CVD oxide and to reduce its wet etch rate. This is done because, unannealed, the CVD oxide has a very low resistance against wet etching and will be damaged in later processing.
While it has its advantages, however, the conventional trench-isolation method does have significant disadvantages as well. As shown in FIGS. 3A to 3C, the polishing step 120 can result in widely varying heights for the silicon nitride layer 5 and the trench-insulating layer 11. FIG. 3A shows a situation where the silicon nitride layer 5 and the trench-insulating layer 11 are polished to a height greater than a desired height; FIG. 3B shows a situation where the silicon nitride layer 5 and the trench-insulating layer 11 are polished at the desired height; and FIG. 3C shows a situation where the silicon nitride layer 5 and the trench-insulating layer 11 are polished to a height lower than a desired height.
This in turn causes problems with the wet etching used in step 30. If the silicon nitride layer 5 and the trench-insulating layer 11 are too high before the wet etching, the trench-insulating layer 11 will remain too high after the wet etching. Similarly, if the silicon nitride layer 5 and the trench-insulating layer 11 are too low before the wet etching, the trench-insulating layer 11 will remain too low after the wet etching. This is illustrated in FIGS. 4A, 4B, and 4C. FIG. 4A shows the results of the wet etching in step 30 if the silicon nitride layer 5 and the trench-insulating layer 11 are too high after the CMP process of step 120; FIG. 4B shows the results of the wet etching in step 30 if the silicon nitride layer 5 and the trench-insulating layer 11 are of the desired height after step 120; and FIG. 4C shows the results of the wet etching in step 30 if the silicon nitride layer 5 and the trench-insulating layer 11 are too low after step 120.
The ultimate result of the variation in heights after the CMP process of step 120 is that the trench isolation structure will have an irregularity in its level, as shown in FIGS. 5A, 5B, and 5C, after the gate electrode 21 has been deposited in step 60. It is, of course, desirable that the gate electrode be level as shown in FIG. 5B, but this only happens if the CMP process of step 120 is done at exactly the right level. If the CMP process leaves the silicon nitride layer 5 and the trench-insulating layer 11 too high, there will be a bump in the trench region that the gate electrode 21 must flow over, as is shown in FIG. 5A. Likewise, if the CMP process leaves the silicon nitride layer 5 and the trench-insulating layer 11 too low, there will be a depression in the trench region that the gate electrode 21 must fill, as is shown in FIG. 5C.
The true problem in these two alternatives is that they place undue stress on the junction where the sidewall-insulating layer 9 and the gate oxide layer 19 meet. This can degrade the performance of the resulting structure by providing imperfect insulation between the gate electrode 21 and the heavily-doped regions 17.
A measure of the stress on this junction can be taken through a time dependent dielectric breakdown (TDDB) test. The TDDB measured by this test gives an indication of the reliability time (in seconds) before gate oxide failure when the proper bias voltage is applied to the gate electrode. In other words, it shows how long you could continually apply the bias voltage to the gate electrode before the device suffers a fatal breakdown. It is generally desirable to keep the TDDB measurement above 100 seconds with an electric field of 15 MV/cm.
As an example, if an entire top surface of the trench isolation region 11 is evenly planarized with the gate oxide region 19, as shown in FIG. 5B, devices have been measured to have TDDB measurements of more than 1200 seconds If, on the other hand, the height of the trench isolation region 11 is depressed compared to the height of the gate oxide region 19, as shown in FIG. 5C, or if the height of the trench isolation region is raised compared to the height of the gate oxide region 19, as shown in FIG. 5A, devices have been measured to have TDDB measurements as low ten seconds. This reliability is too poor for most applications, and seriously reduces the production rates of the manufacturing process.
The reason for this failure can be seen in FIGS. 6A through 6C and FIGS. 7A through 7C. FIGS. 6A through 6C are cross-sectional views showing the interface between the sidewall-insulating layer 9 and the gate oxide 19 for various results of the chemical-mechanical polishing step. FIGS. 7A through 7C are graphs showing the stress distribution of the semiconductor device at the interface between the sidewall-insulating layer 9 and the gate oxide 19 for various results of the chemical-mechanical polishing step.
FIG. 6A shows a semiconductor cross-section and FIG. 7A shows a stress distribution of the semiconductor device where the silicon nitride layer 5 and the trench-insulating layer 11 are polished to a height greater than a desired height. FIG. 6B shows a semiconductor cross-section and FIG. 7B shows a stress distribution of the semiconductor device where the silicon nitride layer 5 and the trench-insulating layer 11 are polish ed at the desired height. FIG. 6C shows a semiconductor cross-section and FIG. 7C shows a stress distribution of the semiconductor device where the silicon nitride layer 5 and the trench-insulating layer 11 are polished to a height lower than a desired height.
As can be seen in FIGS. 6B and 7B, when the trench-insulating layer 11 is formed to be of the desired height, the interface between the sidewall-insulating layer 9 and the gate oxide layer 19 is smooth and the stress generated is relatively low. This lower stress leads to a higher TDDB factor and allows the resulting device to operate within acceptable parameters.
However, as shown in FIGS. 6A and 7A, if the trench-insulating layer 11 is formed too high, the interface between the sidewall-insulating layer 9 and the gate oxide layer 19 is less stable and the stress generated increases. If the trench-insulating layer is too low, the stress will lower the TDDB factor below an acceptable range.
Similarly, as shown in FIGS. 6C and 7C, if the trench-insulating layer 11 is formed too low, the interface between the sidewall-insulating layer 9 and the gate oxide layer 19 is also less stable and the stress generated increases. If the trench-insulating layer is too high, the stress will lower the TDDB factor below an acceptable range.
A greater production reliability is required to improve the yield in the manufacture of trench-isolation semiconductor devices. If the height of the trench-insulating layer 11 cannot be better regulated, it is necessary to improve the performance of the interface between the sidewall-insulating layer 9 and the gate oxide layer 19.